1. Field of the Invention
The present invention relates to integrated circuit memory devices and, in particular, to a decoder circuit that provides a boot-strapped voltage at the output with improved speed and reliability.
2. Discussion of the Prior Art
A decoder is an integrated circuit element used extensively in the selective addressing structure of memory systems, such as dynamic random access memory (DRAM). The decoder selects and activates a particular portion of the memory storage array based on the input address applied to the decoder.
A DRAM typically utilizes a decoder circuit to boot-strap the row lines (or word lines) of the DRAM above the supply voltage in order to restore the full supply voltage into the memory cells.
FIG. 1 shows a conventional DRAM decoder circuit 10 in which a boot-strapped voltage RHX is generated by a boot-strap clock generator 12 and then decoded through boot-strapped predecode circuits 14 which generate row decoder signals R1-R4. Row decoder signals R1-R4 are then distributed throughout the DRAM chip to all of the row decoder circuits 16. The regular predecode signals 17 generated by the regular decoders 18 are routed to the inputs of a dynamic NAND gate (not shown in FIG. 1) in each of the row decoders so that only one row decoder is selected.
As explained in greater detail below, speed is limited in the circuit 10 by the loading on the bootstrap clock generator 12 and the pass transistors and by the loading of the predecode circuits 14. Also, since the boot-strapped voltage RHX must be distributed to all of the row decoders throughout the DRAM chip, the speed to the row decoder physically located the farthest from the boot-strapped predecode circuits 14 will limit the access time of the chip.
In addition, it is necessary in most DRAM designs to use a double boot-strapped node not only in the row decoder circuits 16, but also in the predecode circuits 14. These double boot-strapped nodes are extremely sensitive to leakage and can, therefore, cause reliability problems and degrade the speed of the chip should a leakage path develop.
FIG. 2 shows schematic detail of a conventional row decoder circuit 16. As stated above, the regular predecode lines 17 are the inputs to a dynamic NAND gate 22 which generates a low logic level if this particular row decoder 16 is selected by the input address. An inverter 24 then generates a high level signal in response to the low level input. Since the gates of isolation transistors 26 are connected to the supply voltage Vdd, the source nodes 28 of isolation transistors 26 will only be charged to Vdd-Vtn, where Vtn is the N-channel threshold voltage. After sufficient time to insure that the source nodes 28 of isolation transistors 26 are all charged in the selected decoder, the boot-strap clock generator 12 (FIG. 1) generates signal RHX, which in turn is decoded into signals R1-R4, causing one of the signals R1-R4 to go high and, eventually, to go to a voltage level that is above the supply voltage Vdd.
For purposes of this discussion, assume that signal R1 is selected and goes to a high voltage. As node R1 rises, its voltage level is transferred through N-channel pass transistor 30, since the gate of pass transistor 30 is node 28 and was previously charged to a high level. In addition, however, signal R1 going high causes a boosting effect on node 28 due to the gate-to-drain capacitance of the pass transistor 30. This causes node 28 to rise above the supply voltage Vdd. As signal R1 continues to rise, node 28 also rises higher such that node 28 is always at a higher potential than node R1. The full bootstrapped voltage of node R1 can thus be transferred to word line WL1. The result of this operation is that node 28 is double boot-strapped, since it is at a voltage even higher than the boot-strapped voltage of node R1.
The speed limitation of the above-described conventional decoder circuit 10 arises from the fact that the boosted voltage is generated on the periphery of the chip and has to be routed throughout the chip to all of the row decoders 16. The high going edge of the boosted voltage also must be delayed until the source node 28 of isolation transistor 26 of the worst case decoder is charged. In addition, the boosted voltage must pass through at least two pass transistors to be decoded to the proper word lines (one transistor is pass transistor 30; the other transistor is in the bootstrap predecode circuit shown in FIG. 1). All of these factors combine to inhibit the speed of the device.
In terms of reliability, the double boot-strapped node 28 could become a liability as chip geometries shrink. Care must be taken in the layout and processing of the circuit to insure that this high voltage does not have a leakage path either at time zero or after thousands of hours of use. Should a leakage path develop, the circuit could lose speed and possibly even stop functioning, depending upon the magnitude of the leakage.